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DSP56853/d rev. 4.0 2/2004 ? motorola, inc., 2004. all rights reserved. DSP56853 preliminary technical data DSP56853 16-bit digital signal processor ? 120 mips at 120mhz 12k x 16-bit program sram 4k x 16-bit data sram 1k x 16-bit boot rom access up to 2m words of program memory or 8m of data memory chip select logic for glue-less interface to rom and sram six (6) independent channels of dma enhanced synchronous serial interfaces (essi) two (2) serial communication interfaces (sci) serial port interface (spi) 8-bit parallel host interface general purpose 16-bit quad timer jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging computer operating properly (cop)/watchdog timer time-of-day (tod) 128 lqfp package up to 41 gpio figure 1. DSP56853 block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit dsp56800e core xtal extal interrupt controller quad timer or gpiog 4 clko external address bus switch external bus interface unit 4 reset irqa irqb v dd v ssio v dda v ssa external data bus switch bus control wr enable rd enable cs0-cs3[3:0] or a0-20 [20:0] modea-c or d0-d15 [15:0] 6 program memory 12,288 x 16 sram boot rom 1024 x 16 rom data memory 4,096 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr spi or gpiof 2 sci or gpioe ipbus bridge (ipbb) 3 (gpioh0-h2) 6 10 v ddio 11 decoding peripherals 4 system bus control memory pab pab cdbw cdbr cdbw v ss 6 gpioa0-a3[3:0] 6 essi0 or gpioc host interface or gpiob 16 rsto dma 6 channel por integration module system cop/ watch- dog time of day clock generator osc pll ipbus clk cop/tod clk core clk ipab ipwdb iprdb dma requests f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 DSP56853 technical data preliminary part 1 overview 1.1 DSP56853 features 1.1.1 digital signal processing core efficient 16-bit dsp engine with dual harvard architecture 120 million instructions per second (mips) at 120mhz core frequency single-cycle 16 16-bit parallel multiplier-accumulator (mac) four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter parallel instruction set with unique dsp addressing modes hardware do and rep loops three (3) internal address buses and one (1) external address bus four (4) internal data buses and one (1) external data bus instruction set supports both dsp and controller functions four (4) hardware interrupt levels five (5) software interrupt levels controller-style addressing modes and instructions for compact code efficient c compiler and local variable support software subroutine and interrupt stack with depth limited only by memory jtag/enhanced once debug programming interface 1.1.2 memory harvard architecture permits up to three (3) simultaneous accesses to program and data memory on-chip memory ? 12k 16-bit program sram ? 4k 16-bit data sram ? 1k 16-bit boot rom off-chip memory expansion (emi) ? access up to 2m words of program memory or 8m data memory ? chip select logic for glue-less interface to rom and sram 1.1.3 peripheral circuits for DSP56853 general purpose 16-bit quad timer* two (2) serial communication interfaces (sci)* serial peripheral interface (spi) port* enhanced synchronous serial interface (essi) modules* computer operating properly (cop) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
DSP56853 description DSP56853 technical data 3 preliminary watchdog timer jtag/enhanced on-chip emulation (once) for unobtrusive, real-time debugging six (6) independent channels of dma 8-bit parallel host interface* time-of-day (tod) 128 lqfp package up to 41 gpio * each peripheral i/o can be used alternately as a general purpose i/o if not needed 1.1.4 energy information fabricated in high-density cmos with 3.3v, ttl-compatible digital inputs wait and stop modes available 1.2 DSP56853 description the DSP56853 is a member of the dsp56800e core-based family of digital signal processors (dsps). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the DSP56853 is well-suited for many applications. the DSP56853 includes many peripherals that are especially useful for low-end internet appliance applications and low-end client applications such as telephony; portable devices;; internet audio and point- of-sale systems, such as noise suppression; id tag readers; sonic/subsonic detectors; security access devices; remote metering; sonic alarms. the product family core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers, enabling rapid development of optimized control applications. the DSP56853 supports program execution from either internal or external memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the DSP56853 also provides two external dedicated interrupt lines, and up to 41 general purpose input/output (gpio) lines, depending on peripheral configuration. the DSP56853 dsp controller includes 12k words of program ram, 4k words of data ram, and 1k words of boot rom. it also supports program execution from external memory. the dsp56800 core can access two data operands from the on-chip data ram per instruction cycle. this dsp controller also provides a full set of standard programmable peripherals that include an 8-bit parallel host interface, enhanced synchronous serial interface (essi), one serial peripheral interface (spi), the option to select a second spi or two serial communications interfaces (scis), and quad timer. the host interface, essi, spi, sci, four chip selects and quad timer can be used as general purpose input/ outputs (gpios) if its primary function is not required. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 DSP56853 technical data preliminary 1.3 state of the art development environment processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to- use component-based software application creation with an expert knowledge system. the code warrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards will support concurrent engineering. together, pe, code warrior and evms create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 product documentation the four documents listed in table 1 are required for a complete description of and proper design with the DSP56853. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors/ . table 1. DSP56853 chip documentation 1.5 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800e reference manual detailed description of thedsp56800e architecture, 16-bit dsp core processor and the instruction set dsp56800erm/d DSP56853 user?s manual detailed description of memory, peripherals, and interfaces of the DSP56853 dsp5685xum/d DSP56853 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions DSP56853/d DSP56853 product brief summary description and block diagram of the DSP56853 core, memory, peripherals and interfaces (this document) DSP56853pb/d DSP56853 errata details any chip issues that might be present DSP56853e/d overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for vil, vol, vih, and voh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56853 technical data 5 preliminary part 2 signal/connection descriptions 2.1 introduction the input and output signals of the DSP56853 are organized into functional groups, as shown in table 2 and as illustrated in figure 2 . in table 3 each table row describes the package pin and the signal or signals present. 1. v dd = v dd core, v ss = v ss core, v ddio = v dd io, v ssio = v ss io, v dda = v dd ana, v ssa = v ss ana 2. moda, modb and modc can be used as gpio after the bootstrap process has completed. 3. the following host interface signals are multiplexed: hrwb to hrd , hds to hwr , hreq to htrq and hack to hrrq. table 2. DSP56853 functional group pin allocations functional group number of pins power (v dd, v ddio, or v dda ) (6, 11, 1) 1 ground (v ss, v ssio, or v ssa ) (6, 10, 1) 1 pll and clock 3 external bus signals 39 external chip select* 4 interrupt and program control 7 2 host interface (hi)* 16 3 enhanced synchronous serial interface (essi0) port* 6 serial communications interface (sci0) ports* 2 serial communications interface (sci1) ports* 2 serial peripheral interface (spi) port* 4 quad timer module port* 4 jtag/enhanced on-chip emulation (eonce) 6 *alternately, gpio pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 DSP56853 technical data preliminary . figure 2. DSP56853 signals identified by functional group 2 1. specifically for pll, osc, and por. 2. alternate pin functions are shown in parentheses. DSP56853 logic power i/o power sci 0 jtag / enhanced once timer module essi 0 spi chip select external bus analog power 1 pll/clock host interface sci 2 interrupt/ program control v dd v ss v ddio v ssio v dda v ssa a0 - a20 rd d0 - d15 wr cs0 - cs3 (gpioa0 - a3) hd0 - hd7 (gpiob0 - b7) ha0 - ha2 (gpiob8 - b10) hrwb (hrd ) (gpiob11) hds (hwr ) (gpiob12) hcs (gpiob13) hreq (htrq ) (gpiob14) hack (hrrq) (gpiob15) tio0 - tio3 (gpiog0 - g3) irqa irqb moda, modb, modc (gpioh0 - h2) reset rsto host interface xtal rxdo (gpioe0) txdo (gpioe1) rxd1 (gpioe2) txd1 (gpioe3) std0 (gpioc0) srd0 (gpioc1) sck0 (gpioc2) sc00 (gpioc3) sc01 (gpioc4) sc02 (gpioc5) miso (gpiof0) mosi (gpiof1) sck (gpiof2) ss (gpiof3) extal clko tck tdi tdo tms trst de 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 4 1 1 1 1 1 3 8 4 1 1 16 21 1 1 10 11 6 6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56853 technical data 7 preliminary part 3 signals and package information all digital inputs have a weak internal pull-up circuit associated with them. these pull-up circuits are enabled by default. exceptions: 1. when a pin has gpio functionality, the pull-up may be disabled under software control. 2. mode a, mode b and mode c pins have no pull-up. 3. tck has a weak pull-down circuit always active. 4. bidirectional i/o pullups automatically disable when the output is enabled. this table is presented consistently with the signals identified by functional group figure. 1. bold entries in the type column represents the state of the pin just out of reset. 2. ouput(z) means an output in a high-z condition table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description 13 v dd v dd power (v dd ) ? these pins provide power to the internal structures of the chip, and should all be attached to v dd. 47 v dd 64 v dd 79 v dd 80 v dd 112 v dd 14 v ss v ss ground (v ss ) ? these pins provide grounding for the internal structures of the chip and should all be attached to v ss. 48 v ss 63 v ss 81 v ss 96 v ss 113 v ss 5v ddio v ddio power (v ddio ) ? these pins provide power for all i/o and esd structures of the chip, and should all be attached to v ddio (3.3v) . 18 v ddio 41 v ddio 55 v ddio 61 v ddio 72 v ddio 91 v ddio 92 v ddio 100 v ddio 114 v ddio 124 v ddio f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 DSP56853 technical data preliminary 6v ssio v ssio ground (v ssio ) ? these pins provide grounding for all i/o and esd structures of the chip and should all be attached to v ss. 19 v ssio 42 v ssio 56 v ssio 62 v ssio 74 v ssio 93 v ssio 102 v ssio 115 v ssio 125 v ssio 22 v dda v dda analog power (v dda ) ? these pins supply an analog power source. 23 v ssa v ssa analog ground (v ssa ) ? this pin supplies an analog ground. 9a0 output(z) address bus (a0-a20) ? these signals specify a word address for external program or data memory access. 10 a1 11 a2 12 a3 26 a4 27 a5 28 a6 29 a7 43 a8 44 a9 45 a10 46 a11 57 a12 58 a13 59 a14 60 a15 67 a16 68 a17 69 a18 70 a19 71 a20 table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56853 technical data 9 preliminary 73 d0 input /output(z) data bus (d0-d15) ? these pins provide the bidirectional data for external program or data memory accesses. 86 d1 87 d2 88 d3 89 d4 90 d5 107 d6 108 d7 109 d8 110 d9 111 d10 122 d11 123 d12 126 d13 127 d14 128 d15 7rd output read enable (rd ) ? is asserted during external memory read cycles. this signal is pulled high during reset. 8wr output write enable (wr ) ? is asserted during external memory write cycles. this signal is pulled high during reset. 75 cs0 gpioa0 output input /output external chip select (cs0 ) ? this pin is used as a dedicated gpio. port a gpio (0 ) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 76 cs1 gpioa1 output input /output external chip select (cs1 ) ? this pin is used as a dedicated gpio. port a gpio (1) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 77 cs2 gpioa2 output input /output external chip select (cs2 ) ? this pin is used as a dedicated gpio. port a gpio (2) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 78 cs3 gpioa3 output input /output external chip select (cs3 ) ? this pin is used as a dedicated gpio. port a gpio (3) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 DSP56853 technical data preliminary 30 hd0 gpiob0 input input/output host address (hd0)? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (0) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 31 hd1 gpiob1 input input/output host address (hd1)? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (1) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 32 hd2 gpiob2 input input/output host address (hd2) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (2) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 36 hd3 gpiob3 input input/output host address (hd3) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (3) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 37 hd4 gpiob4 input input/output host address (hd4) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (4) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 38 hd5 gpiob5 input input/output host address (hd5) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (5) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 39 hd6 gpiob6 input input/output host address (hd6) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (6) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56853 technical data 11 preliminary 40 hd7 gpiob7 input input/output host address (hd7) ? this input provides data selection for hi registers. this pin is disconnected internally during reset. port b gpio (7) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 82 ha0 gpiob8 input input/output host address (ha0) ? these inputs provide the address selection for hi registers. these pins are disconnected internally during reset. port b gpio (8) ? these pins are general purpose i/o (gpio) pins when not configured for host port usage. 83 ha1 gpiob9 input input/output host address (ha0) ? these inputs provide the address selection for hi registers. these pins are disconnected internally during reset. port b gpio (9) ? these pins are general purpose i/o (gpio) pins when not configured for host port usage. 84 ha2 gpiob10 input input/output host address (ha0) ? these inputs provide the address selection for hi registers. these pins are disconnected internally during reset. port b gpio (10) ? these pins are general purpose i/o (gpio) pins when not configured for host port usage. 85 hrwb hrd gpiob11 input input input/output host read/write (hrwb) ? when the hi08 is programmed to interface to a single-data-strobe host bus and the hi function is selected, this signal is the read/write input. these pins are disconnected internally. host read data (hrd ) ? this signal is the read data input when the hi08 is programmed to interface to a double-data- strobe host bus and the hi function is selected. port b gpio (11) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 103 hds hwr gpiob12 input input input/output host data strobe (hds ) ? when the hi08 is programmed to interface to a single-data-strobe host bus and the hi function is selected, this input enables a data transfer on the hi when hcs is asserted. these pins are disconnected internally. host write enable (hwr ) ? this signal is the write data input when the hi08 is programmed to interface to a double- data-strobe host bus and the hi function is selected. port b gpio (12) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12 DSP56853 technical data preliminary 104 hcs gpiob13 input input/output host chip select (hcs ) ? this input is the chip select input for the host interface. these pins are disconnected internally. port b gpio (13) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 105 hreq htrq gpiob14 open drain output open drain output input/output host request (hreq ) ? when the hi08 is programmed for hrms=0 functionality (typically used on a single-data-strobe bus), this open drain output is used by the hi to request service from the host processor. the hreq may be connected to an interrupt request pin of a host processor, a transfer request of a dma controller, or a control input of external circuitry. these pins are disconnected internally. transmit host request (htrq ) ? this signal is the transmit host request output when the hi08 is programmed for hrms=1 functionality and is typically used on a double- data-strobe bus. port b gpio (14) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 106 hack hrrq gpiob15 input open drain output input/output host acknowledge (hack ) ? when the hi08 is programmed for hrms=0 functionality (typically used on a single-data-strobe bus), this input has two functions: (1) provide a host acknowledge signal for dma transfers or (2) to control handshaking and provide a host interrupt acknowledge compatible with the mc68000 family processors. these pins are disconnected internally. receive host request (hrrq) ? this signal is the receive host request output when the hi08 is programmed for hrms=1 functionality and is typically used on a double-data- strobe bus. port b gpio(15) ? this pin is a general purpose i/o (gpio) pin when not configured for host port usage. 101 tio0 gpiog0 input /output input/output timer input/outputs (tio0) ? this pin can be independently configured to be either a timer input source or an output flag. port g gpiog0 ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. 99 tio1 gpiog1 input /output input/output timer input/outputs (tio1) ? this pin can be independently configured to be either a timer input source or an output flag. port g gpio (1) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56853 technical data 13 preliminary 98 tio2 gpiog2 input /output input/output timer input/outputs (tio2) ? this pin can be independently configured to be either a timer input source or an output flag. port g gpio (2) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. 97 tio3 gpiog3 input /output input/output timer input/outputs (tio3) ? this pin can be independently configured to be either a timer input source or an output flag. port g gpio (3) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as an input or output pin. 20 irqa input external interrupt request a and b ? the irqa and irqb inputs are asynchronous external interrupt requests that indicate that an external device is requesting service. a schmitt trigger input is used for noise immunity. they can be programmed to be level-sensitive or negative-edge- triggered. if level-sensitive triggering is selected, an external pull-up resistor is required for wired-or operation. 21 irqb 15 moda gpioh0 input input/output mode select (moda) ? during the bootstrap process moda selects one of the eight bootstrap modes. port h gpio (0) ? this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. 16 modb gpioh1 input input/output mode select (modb) ? during the bootstrap process modb selects one of the eight bootstrap modes. port h gpio (1) ? this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. 17 modc gpioh2 input input/output mode select (modc) ? during the bootstrap process modc selects one of the eight bootstrap modes. port h gpio (2) ? this pin is a general purpose i/o (gpio) pin after the bootstrap process has completed. 35 reset input reset (reset ) ? this input is a direct hardware reset on the processor. when reset is asserted low, the dsp is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the moda, modb, and modc pins. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware dsp reset is required and it is necessary not to reset the jtag/enhanced once module. in this case, assert reset , but do not assert trst . 34 rsto output reset output (rsto ) ? this output is asserted on any reset condition (external reset, low voltage, software or cop). table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14 DSP56853 technical data preliminary 65 rxd0 gpioe0 input input/output serial receive data 0 (rxd0) ? this input receives byte- oriented serial data and transfers it to the sci 0 receive shift register. port e gpio (0) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 66 txd0 gpioe1 output(z) input/output serial transmit data 0 (txd0) ? this signal transmits data from the sci 0 transmit data register. port e gpio (1) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 94 rxd1 gpioe2 input input/output serial receive data 1 (rxd1) ? this input receives byte- oriented serial data and transfers it to the sci 1 receive shift register. port e gpio (2) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 95 txd1 gpioe3 output(z) input/output serial transmit data 1 (txd1) ? this signal transmits data from the sci 1 transmit data register. port e gpio (3) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 116 std0 gpioc0 output input /output essi transmit data (std0) ? this output pin transmits serial data from the essi transmitter shift register. port c gpio (0) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. 117 srd0 gpioc1 input input /output essi receive data (srd0) ? this input pin receives serial data and transfers the data to the essi receive shift register. port c gpio (1) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. 118 sck0 gpioc2 input /output input/output essi serial clock (sck0) ? this bidirectional pin provides the serial bit rate clock for the transmit section of the essi. the clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. port c gpio (2) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56853 technical data 15 preliminary 119 sc00 gpioc3 input /output input/output essi serial control pin 0 (sc00) ? the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin will be used for the receive clock i/o. for synchronous mode, this pin is used either for transmitter1 output or for serial i/o flag 0. port c gpio (3) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. 120 sc01 gpioc4 input /output input/output essi serial control pin 1 (sc01) ? the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin is the receiver frame sync i/o. for synchronous mode, this pin is used either for transmitter2 output or for serial i/o flag 1. port c gpio (4) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. 121 sc02 gpioc5 input /output input /output essi serial control pin 2 (sc02) ? this pin is used for frame sync i/o. sc02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this pin is the internally generated frame sync signal. when configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port c gpio (5) ? this pin is a general purpose i/o (gpio) pin when the essi is not in use. 1miso gpiof0 input /output input/output spi master in/slave out (miso) ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high- impedance state if the slave device is not selected. the driver on this pin can be configured as an open-drain driver by the spi ? s wired-or mode (wom) bit when this pin is configured for spi operation. port f gpio (0) ? this pin is a general purpose i/o (gpio) pin that can be individually programmed as input or output pin. 2mosi gpiof1 input /output (z) input/output spi master out/slave in (mosi) ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge that the slave device uses to latch the data. the driver on this pin can be configured as an open- drain driver by the spi ? s wom bit when this pin is configured for spi operation. port f gpio (1) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16 DSP56853 technical data preliminary 3sck gpiof2 input /output input/output spi serial clock (sck) ? this bidirectional pin provides a serial bit rate clock for the spi. this gated clock signal is an input to a slave device and is generated as an output by a master device. slave devices ignore the sck signal unless the ss pin is active low. in both master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge, where data is stable. the driver on this pin can be configured as an open-drain driver by the spi ? s wom bit when this pin is configured for spi operation. when using wired-or mode, the user must provide an external pull-up device. port f gpio (2) ? this pin is a general purpose i/o (gpio) pin that can be individually programmed as input or output pin. 4ss gpiof3 input input/output spi slave select (ss ) ? this input pin selects a slave device before a master device can exchange data with the slave device. ss must be low before data transactions and must stay low for the duration of the transaction. the ss line of the master must be held high. port f gpio (3) ? this pin is a general purpose i/o (gpio) pin that can individually be programmed as input or output pin. 24 xtal input/ output crystal oscillator output (xtal) ? this output connects the internal crystal oscillator output to an external crystal. if an external clock source other than a crystal oscillator is used, xtal must be used as the input. 25 extal input external crystal oscillator input (extal) ? this input should be connected to an external crystal. if an external clock source other than a crystal oscillator is used, extal must be tied off. see section 4.5.2 33 clko output clock output (clko) ? this pin outputs a buffered clock signal. when enabled, this signal is the system clock divided by four. 54 tck input test clock input (tck) ? this input pin provides a gated clock to synchronize the test logic and to shift serial data to the jtag/enhanced once port. the pin is connected internally to a pull-down resistor. 52 tdi input test data input (tdi) ? this input pin provides a serial input data stream to the jtag/enhanced once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 51 tdo output (z) test data output (tdo) ? this tri-statable output pin provides a serial output data stream from the jtag/ enhanced once port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. 53 tms input test mode select input (tms) ? this input pin is used to sequence the jtag tap controller ? s state machine. it is sampled on the rising edge of tck and has an on-chip pull- up resistor. table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction DSP56853 technical data 17 preliminary 50 trst input test reset (trst ) ? as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment, since the enhanced once/jtag module is under the control of the debugger. in this case it is not necessary to assert trst when asserting reset . outside of a debugging environment reset should be permanently asserted by grounding the signal, thus disabling the enhanced once/jtag module on the dsp. 49 de input /output debug event (de ) ? this is an open-drain, bidirectional, active low signal. as an input, it is a means of entering debug mode of operation from an external command controller. as an output, it is a means of acknowledging that the chip has entered debug mode. this pin is connected internally to a weak pull-up resistor. table 3. DSP56853 signal and package information for the 128-pin lqfp pin no. signal name type description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18 DSP56853 technical data preliminary part 4 specifications 4.1 general characteristics the DSP56853 is fabricated in high-density cmos with 5-volt tolerant ttl-compatible digital inputs. the term ? 5-volt tolerant ? refers to the capability of an i/o pin, built on a 3.3v compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v and 5v- compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v tolerant capability therefore offers the power savings of 3.3v i/o levels while being able to receive 5v levels without being damaged. absolute maximum ratings given in table 4 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the DSP56853 dc/ac electrical specifications are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterization and device qualifications have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 4. absolute maximum ratings characteristic symbol min max unit supply voltage, core v dd 1 1. v dd must not exceed v ddio v ss ? 0.3 v ss + 2.0 v supply voltage, io supply voltage, analog v ddio 2 v ddio 2 2. v ddio and v dda must not differ by more that 0.5v v ssio ? 0.3 v ssa ? 0.3 v ssio + 4.0 v dda + 4.0 v digital input voltages analog input voltages (xtal, extal) v in v ina v ssio ? 0.3 v ssa ? 0.3 v ssio + 5.5 v dda + 0.3 v current drain per pin excluding v dd , gnd i ? 8 ma junction temperature t j -40 120 c storage temperature range t stg -55 150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general characteristics DSP56853 technical data 19 preliminary table 5. recommended operating conditions characteristic symbol min max unit supply voltage for logic power v dd 1.62 1.98 v supply voltage for i/o power v ddio 3.0 3.6 v supply voltage for analog power v dda 3.0 3.6 v ambient operating temperature t a -40 85 c pll clock frequency 1 1. assumes clock source is direct clock to extal or crystal oscillator running 2-4mhz. pll must be enabled, locked, and selected. the actual frequency depends on the source clock frequency and programming of the cgm module. f pll ? 240 mhz operating frequency 2 2. master clock is derived from on of the following four sources: f clk = f xtal when the source clock is the direct clock to extal f clk = f pll when pll is selected f clk = f osc when the source clock is the crystal oscillator and pll is not selected f clk = f extal when the source clock is the direct clock to extal and pll is not selected f op ? 120 mhz frequency of peripheral bus f ipb ? 60 mhz frequency of external clock f clk ? 240 mhz frequency of oscillator f osc 24mhz frequency of clock via xtal f xtal ? 240 mhz frequency of clock via extal f extal 24mhz table 6. thermal characteristics 1 1. see section 6.1 for more detail. characteristic 128-pin lqfp symbol value unit thermal resistance junction-to-ambient (estimated) ja 43.1 c/w i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd v dd ) + p i/o w maximum allowed p d p dmax (t j ? t a ) / ja c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20 DSP56853 technical data preliminary 4.2 dc electrical characteristics table 7. dc electrical characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc v dda ? 0.8 v dda v dda + 0.3 v input low voltage (xtal/extal) v ilc -0.3 ? 0.5 v input high voltage v ih 2.0 ? 5.5 v input low voltage v il -0.3 ? 0.8 v input current low (pullups disabled) i il -1 ? 1 a input current high (pullups disabled) i ih -1 ? 1 a output tri-state current low i ozl -10 ? 10 a output tri-state current high i ozh -10 ? 10 a output high voltage v oh v dd ? 0.7 ?? v output low voltage v ol ?? 0.4 v output high current i oh 8 ? 16 ma output low current i ol 8 ? 16 ma input capacitance c in ? 8 ? pf output capacitance c out ? 12 ? pf v dd supply current (core logic, memories, peripherals) run 1 deep stop 2 light stop 3 1. running core, performing 50% nop and 50% fir. clock at 120 mhz. 2. deep stop mode - operation frequency = 4 mhz, pll set to 4 mhz, crystal oscillator and time of day module oper- ating. 3. light stop mode - operation frequency = 120 mhz, pll set to 240 mhz, crystal oscillator and time of day module op- erating. i dd 4 4. i dd includes current for core logic, internal memories, and all internal peripheral logic circuitry. ? ? ? 70 0.05 5 110 10 14 ma ma ma v ddio supply current (i/o circuity) run 5 deep stop 2 5. running core and performing external memory access. clock at 120 mhz. i ddio ? 40 0 50 1.5 ma ma v dda supply current (analog circuity) deep stop 2 i dda ? 60 120 a low voltage interrupt 6 6. when v dd drops below v ei max value, an interrupt is generated. v ei ? 2.5 2.85 v low voltage interrupt recovery hysteresis v eih ? 50 ? mv power on reset 7 7. power-on reset occurs whenever the digital supply drops below 1.8v. while power is ramping up, this signal remains active for as long as the internal 2.5v is below 1.8v no matter how long the ramp up rate is. the internally regulated volt- age is typically 100 mv less than v dd during ramp up until 2.5v is reached, at which time it self-regulates. por ? 1.5 2.0 v note: run (operating) i dd measured using external square wave clock source (f osc = 4mhz) into xtal. all inputs 0.2v from rail; no dc loads; outputs unloaded. all ports configured as inputs; measured with all modules enabled. pll set to 240mhz out. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
supply voltage sequencing and separation cautions DSP56853 technical data 21 preliminary figure 3. maximum run i ddtotal vs. frequency (see notes 1. and 5. in table 7 ) 4.3 supply voltage sequencing and separation cautions figure 1 shows two situations to avoid in sequencing the v dd and v ddio, v dda supplies. notes: 1. v dd rising before v ddio , v dda 2. v ddio , v dda rising much faster than v dd figure 4. supply voltage sequencing and separation cautions 0 30 60 120 150 20 40 60 80 100 120 idd (ma) 90 emi mode 5 mac mode 1 3.3v 1.8v time 0 2 1 supplies stable v dd v ddio, v dda dc power supply voltage f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
22 DSP56853 technical data preliminary v dd should not be allowed to rise early (1). this is usually avoided by running the regulator for the v dd supply (1.8v) from the voltage generated by the 3.3v v ddio supply, see figure 2 . this keeps v dd from rising faster than v ddio . v dd should not rise so late that a large voltage difference is allowed between the two supplies (2). typically this situation is avoided by using external discrete diodes in series between supplies, as shown in figure 2 . the series diodes forward bias when the difference between v ddio and v dd reaches approximately 2.1, causing v dd to rise as v ddio ramps up. when the v dd regulator begins proper operation, the difference between supplies will typically be 0.8v and conduction through the diode chain reduces to essentially leakage current. during supply sequencing, the following general relationship should be adhered to: v ddio > v dd > (v ddio - 2.1v) in practice, v dda is typically connected directly to v ddio with some filtering. figure 5. example circuit to control supply sequencing 4.4 ac electrical characteristics timing waveforms in section 4.2 are tested with a v il maximum of 0.8 v and a v ih minimum of 2.0 v for all pins except xtal, which is tested using the input levels in section 4.2 . in figure 6 the levels of v ih and v il for an input signal are shown. figure 6. input signal measurement references figure 7 shows the definitions of the following signal states: active state, when a bus or signal is driven, and enters a low impedance state. tri-stated, when a bus or signal is placed in a high impedance state. data valid state, when a signal level has reached v ol or v oh. data invalid state, when a signal level is in transition between v ol and v oh. 3.3v regulator 1.8v regulator supply v dd v ddio, v dda v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
external clock operation DSP56853 technical data 23 preliminary 4.5 external clock operation the DSP56853 system clock can be derived from a crystal or an external system clock signal. to generate a reference frequency using the internal oscillator, a reference crystal must be connected between the extal and xtal pins. 4.5.1 crystal oscillator the internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in table 9 . in figure 8 a typical crystal oscillator circuit is shown. follow the crystal supplier ? s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. the crystal and associated components should be mounted as close as possible to the extal and xtal pins to minimize output distortion and start-up stabilization time. figure 8. crystal oscillator 4.5.2 high speed external clock source (> 4mhz) the recommended method of connecting an external clock is given in figure 9 . the external clock source is connected to xtal and the extal pin is held at ground, v dda , or v dda /2. the tod_sel bit in cgm must be set to 0. figure 7. signal states data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active sample external crystal parameters: r z = 10m ? tod_sel bit in cgm must be set to 0 crystal frequency = 2 ? 4 mhz (optimized for 4mhz) extal xtal r z f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
24 DSP56853 technical data preliminary figure 9. connecting a high speed external clock signal using xtal 4.5.3 low speed external clock source (2-4mhz) the recommended method of connecting an external clock is given in figure 10 . the external clock source is connected to xtal and the extal pin is held at v dda /2. the tod_sel bit in cgm must be set to 0. figure 10. connecting a low speed external clock signal using xtal table 8. external clock operation timing requirements 4 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit frequency of operation (external clock driver) 1 1. see figure 9 for details on using the recommended connection of an external clock driver. f osc 0 ? 240 mhz clock pulse width 4 t pw 6.25 ?? ns external clock input rise time 2, 4 2. external clock input rise time is measured from 10% to 90%. t rise ?? tbd ns external clock input fall time 3, 4 3. external clock input fall time is measured from 90% to 10%. 4. parameters listed are guaranteed by design. t fall ?? tbd ns DSP56853 xtal extal external gnd, v dda , clock (up to 240mhz) or v dda /2 DSP56853 xtal extal external clock (2-4mhz) v dda /2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
external memory interfacetiming DSP56853 technical data 25 preliminary figure 11. external clock timing 4.6 external memory interfacetiming the external memory interface is designed to access static memory and peripheral devices. figure 12 shows sample timing and parameters that are detailed in table 10 . the timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user controlled wait states. the equation: t = d + p * (m + w) should be used to determine the actual time of each parameter. the terms in the above equation are defined as: t parameter delay time d fixed portion of the delay, due to on-chip path delays. p the period of the system clock, which determines the execution rate of the part (i.e. when the device is operating at 120 mhz, p = 8.33 ns). m fixed portion of a clock period inherent in the design. this number is adjusted to account for possible clock duty cycle derating. w the sum of the applicable wait state controls. see the ? wait state controls ? column of table 10 for the applicable controls for each parameter. see the emi chapter of the 83x peripheral manual for details of what each wait state field controls. some of the parameters contain two sets of numbers. these parameters have two different paths and clock edges that must be considered. check both sets of numbers and use the smaller result. the appropriate entry may change if the operating frequency of the part changes. the timing of write cycles is different when wws = 0 than when wws > 0. therefore, some parameters contain two sets of numbers to account for this difference. the ? wait states configuration ? column of table 10 should be used to make the appropriate selection. table 9. pll timing operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min typ max unit external reference crystal frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 4mhz input crystal. f osc 244mhz pll output frequency f clk 40 ? 240 mhz pll stabilization time 2 2. this is the minimum time required after the pll setup is changed to ensure reliable operation. t plls ? 110ms external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
26 DSP56853 technical data preliminary figure 12. external memory interface timing table 10. external memory interface timing operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98 v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, p = 8.333ns characteristic symbol wait states configuration dm wait states controls unit address valid to wr asserted t awr wws=0 -0.79 0.50 wwss ns wws>0 -1.98 0.69 wr width asserted to wr deasserted t wr wws=0 -0.86 0.19 wws ns wws>0 -0.01 0.00 data out valid to wr asserted t dwr wws=0 -1.52 0.00 wwss ns wws=0 - 5.69 0.25 wws>0 -2.10 0.19 wws>0 -4.66 0.50 valid data out hold time after wr deasserted t doh -1.47 0.25 wwsh ns valid data out set up time to wr deasserted t dos -2.36 0.19 wws,wwss ns -4.67 0.50 valid address after wr deasserted t wac -1.60 0.25 wwsh rd deasserted to address invalid t rda - 0.44 0.00 rwsh ns address valid to rd deasserted t ardd -2.07 1.00 rwss,rws ns valid input data hold after rd deasserted t drd 0.00 n/a 1 ? ns t drd t rdd t ad t doh t dos t dwr t rdwr t wac t wrrd t wr t awr t wrwr t ardd t rda t rdrd t rd t arda data out data in a0-axx,cs rd wr d0-d15 note: during read-modify-write instructions and internal instructions, the address lines do not change state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reset, stop, wait, mode select, and interrupt timing DSP56853 technical data 27 preliminary 4.7 reset, stop, wait, mode select, and interrupt timing rd assertion width t rd -1.34 1.00 rws ns address valid to input data valid t ad -10.27 1.00 rwss,rws ns -13.5 1.19 address valid to rd asserted t arda - 0.94 0.00 rwss ns rd asserted to input data valid t rdd -9.53 1.00 rwss,rws ns -12.64 1.19 wr deasserted to rd asserted t wrrd -0.75 0.25 wwsh,rwss ns rd deasserted to rd asserted t rdrd -0.16 2 0.00 rwss,rwsh ns wr deasserted to wr asserted t wrwr wws=0 -0.44 0.75 wwss, wwsh ns wws>0 -0.11 1.00 rd deasserted to wr asserted t rdwr 0.14 0.50 mdar, bmdar, rwsh, wwss ns -0.57 0.69 1. n/a since device captures data before it deasserts rd 2. if rwss = rwsh = 0, rd does not deassert during back-to-back reads and d=0.00 should be used. table 11. reset, stop, wait, mode select, and interrupt timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit see figure reset assertion to address, data and control signals high impedance t raz ? 11 ns figure 13 minimum reset assertion duration 3 t ra 30 ? ns figure 13 reset deassertion to first external address output t rda ? 120t ns figure 13 edge-sensitive interrupt request width t irw 1t + 3 ? ns figure 14 irqa , irqb assertion to external data memory access out valid, caused by first instruction execution in the interrupt service routine t idm 18t ? ns figure 15 t idm -fast 14t ? irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig 18t ? ns figure 15 t ig -fast 14t ? table 10. external memory interface timing (continued) operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98 v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, p = 8.333ns characteristic symbol wait states configuration dm wait states controls unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
28 DSP56853 technical data preliminary irqa low to first valid interrupt vector address out recovery from wait state 4 t iri 22t ? ns figure 16 t iri -fast 18t ? delay from irqa assertion (exiting stop) to external data memory 5 t iw 1.5t ? ns figure 17 delay from irqa assertion (exiting wait) to external data memory fast 6 normal 7 t if 18t 22et ? ? ns ns figure 17 rsto pulse width 8 normal operation internal reset mode t rsto 128et 8et ? ? ? ? figure 18 1. in the formulas, t = clock cycle. for f op = 120mhz operation and f ipb = 60mhz, t = 8.33ns. 2. parameters listed are guaranteed by design. 3. at reset, the pll is disabled and bypassed. the part is then put into run mode and t clk assumes the period of the source clock, t xtal , t extal or t osc . 4. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the stop state. this is not the minimum required so that the irqa interrupt is accepted. 5. the interrupt instruction fetch is visible on the pins only in mode 3. 6. fast stop mode: fast stop recovery applies when external clocking is in use (direct clocking to xtal) or when fast stop mode recovery is requested (omr bit 6 is set to 1). in both cases the pll and the master clock are unaffected by stop mode entry. recovery takes one less cycle and t clk will continue same value it had before stop mode was entered. 7. normal stop mode: as a power saving feature, normal stop mode disables and bypasses the pll. stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and t clk will resume at the input clock source rate. 8. et = external clock period, for an external crystal frequency of 8mhz, et=125 ns. table 11. reset, stop, wait, mode select, and interrupt timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit see figure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
reset, stop, wait, mode select, and interrupt timing DSP56853 technical data 29 preliminary figure 13. asynchronous reset timing figure 14. external interrupt timing (negative-edge-sensitive) figure 15. external level-sensitive interrupt timing figure 16. interrupt from wait state timing first fetch a0 ? a20, d0 ? d15 cs , rd , wr reset first fetch t rda t ra t raz irqa irqb t irw a0 ? a20, cs , rd , wr irqa , irqb first interrupt instruction execution a) first interrupt instruction execution purpose i/o pin irqa , irqb b) general purpose i/o t ig t idm general instruction fetch irqa , irqb first interrupt vector a0 ? a20, cs , rd , wr t iri f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
30 DSP56853 technical data preliminary figure 17. recovery from stop state using asynchronous interrupt timing figure 18. reset output timing not irqa interrupt vector irqa a0 ? a20, cs , rd , wr first instruction fetch t iw t if reset t rsto f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
host interface port DSP56853 technical data 31 preliminary 4.8 host interface port figure 19. dsp-to-host dma read mode table 12. host interface port timing 1 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. the formulas: t = clock cycle. f ipb = 60mhz, t = 16.7ns. characteristic symbol min max unit see figure access time tackdv ? 13 ns figure 19 disable time tackdz 3 ? ns figure 19 time to disassert tackreqh 3.5 9 ns figure 19 figure 22 lead time treqackl 0 ? ns figure 19 figure 22 access time tradv ? 13 ns figure 20 figure 21 disable time tradx 5 ? ns figure 20 figure 21 disable time tradz 3 ? ns figure 20 figure 21 setup time tdacks 3 ? ns figure 22 hold time tackdh 1 ? ns figure 22 setup time tadss 3 ? ns figure 23 figure 24 hold time tdsah 1 ? ns figure 23 figure 24 pulse width twds 5 ? ns figure 23 figure 24 time to re-assert 1. after second write in 16-bit mode 2. after first write in 16-bit mode or after write in 8-bit mode tackreql 4t + 5 5 5t + 9 13 ns ns figure 19 , figure 22 hack hd hreq tackdv tackdz treqackl tackreql tackreqh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
32 DSP56853 technical data preliminary figure 20. single strobe read mode figure 21. dual strobe read mode tradv tradz tradx ha hcs hds hd hrw tradv tradz tradx ha hcs hwr hd hrd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
host interface port DSP56853 technical data 33 preliminary figure 22. host-to-dsp dma write mode figure 23. single strobe write mode figure 24. dual strobe write mode hack hreq hd tdacks tackdh treqackl tackreql tackreqh ha hcs hds hd hrw tadss tadss tdsah tdsah twds tdsah ha hcs hwr hd hrd twds tadss tadss tdsah f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34 DSP56853 technical data preliminary 4.9 serial peripheral interface (spi) timing 1. parameters listed are guaranteed by design. table 13. spi timing 1 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit see figure cycle time master slave t c 25 25 ? ? ns ns figures 25 , 26 , 27 , 28 enable lead time master slave t eld ? 12.5 ? ? ns ns figure 28 enable lag time master slave t elg ? 12.5 ? ? ns ns figure 28 clock (sclk) high time master slave t ch 9 12.5 ? ? ns ns figures 25 , 26 , 27 , 28 clock (sclk) low time master slave t cl 12 12.5 ? ? ns ns figure 28 data set-up time required for inputs master slave t ds 10 2 ? ? ns ns figures 25 , 26 , 27 , 28 data hold time required for inputs master slave t dh 0 2 ? ? ns ns figures 25 , 26 , 27 , 28 access time (time to data active from high-impedance state) slave t a 515 ns ns figure 28 disable time (hold time to high-impedance state) slave t d 29 ns ns figure 28 data valid for outputs master slave (after enable edge) t dv ? ? 2 14 ns ns figures 25 , 26 , 27 , 28 data invalid master slave t di 0 0 ? ? ns ns figures 25 , 26 , 27 , 28 rise time master slave t r ? ? 11.5 10.0 ns ns figures 25 , 26 , 27 , 28 fall time master slave t f ? ? 9.7 9.0 ns ns figures 25 , 26 , 27 , 28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial peripheral interface (spi) timing DSP56853 technical data 35 preliminary figure 25. spi master timing (cpha = 0) figure 26. spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14 ? 1lsb in master msb out bits 14 ? 1 master lsb out ss (input) ss is held high on master t c t r t f t ch t cl t f t r t ch t ch t dv t dh t ds t di t di (ref) t f t r t cl sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14 ? 1lsb in master msb out bits 14 ? 1 master lsb out ss (input) ss is held high on master t r t f t c t ch t cl t ch t cl t f t ds t dh t r t di t dv (ref) t dv t f t r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
36 DSP56853 technical data preliminary figure 27. spi slave timing (cpha = 0) figure 28. spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14 ? 1 msb in bits 14 ? 1 lsb in ss (input) slave lsb out t ds t cl t cl t di t di t ch t ch t r t r t elg t dh t eld t c t f t f t d t a t dv sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14 ? 1 msb in bits 14 ? 1lsb in ss (input) slave lsb out t elg t di t ds t dh t eld t c t cl t ch t r t f t f t cl t ch t dv t a t dv t r t d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
quad timer timing DSP56853 technical data 37 preliminary 4.10 quad timer timing figure 29. timer timing table 14. quad timer timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas listed, t = clock cycle. for f op = 120mhz operation and fipb = 60mhz, t = 8.33ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit timer input period p in 2t + 3 ? ns timer input high/low period p inhl 1t + 3 ? ns timer output period p out 2t - 3 ? ns timer output high/low period p outhl 1t - 3 ? ns timer inputs timer outputs p inhl p inhl p in p outhl p outhl p out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
38 DSP56853 technical data preliminary 4.11 enhanced synchronous serial interface (essi) timing table 15. essi master mode 1 switching characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. master mode is internally generated clocks and frame syncs parameter symbol min typ max units sck frequency fs ?? 15 2 2. max clock frequency is ip_clk/4 = 60mhz / 4 = 15mhz for an 120mhz part. mhz sck period 3 3. all the timings for the essi are given for a non-inverted serial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal sck/sc0 and/or the frame sync sc2/sc1 in the tables and in the figures. t sckw 66.7 ?? ns sck high time t sckh 33.4 4 4. 50 percent duty cycle ?? ns sck low time t sckl 33.4 4 ?? ns output clock rise/fall time ?? 4 ? ns delay from sck high to sc2 (bl) high - master 5 5. bl = bit length; wl = word length t tfsbhm -1.0 ? 1.0 ns delay from sck high to sc2 (wl) high - master 5 t tfswhm -1.0 ? 1.0 ns delay from sc0 high to sc1 (bl) high - master 5 t rfsbhm -1.0 ? 1.0 ns delay from sc0 high to sc1 (wl) high - master 5 t rfswhm -1.0 ? 1.0 ns delay from sck high to sc2 (bl) low - master 5 t tfsblm -1.0 ? 1.0 ns delay from sck high to sc2 (wl) low - master 5 t tfswlm -1.0 ? 1.0 ns delay from sc0 high to sc1 (bl) low - master 5 t rfsblm -1.0 ? 1.0 ns delay from sc0 high to sc1 (wl) low - master 5 t rfswlm -1.0 ? 1.0 ns sck high to std enable from high impedance - master t txem -0.1 ? 2ns sck high to std valid - master t txvm -0.1 ? 2ns sck high to std not valid - master t txnvm -0.1 ?? ns sck high to std high impedance - master t txhim -4 ? 0ns srd setup time before sc0 low - master t sm 4 ?? ns srd hold time after sc0 low - master t hm 4 ?? ns synchronous operation (in addition to standard internal clock parameters) srd setup time before sck low - master t tsm 4 ?? ns srd hold time after sck low - master t thm 4 ?? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
enhanced synchronous serial interface (essi) timing DSP56853 technical data 39 preliminary figure 30. master mode timing diagram table 16: essi slave mode 1 switching characteristics operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units sck frequency fs ?? 15 2 mhz sck period 3 t sckw 66.7 ?? ns sck high time t sckh 33.4 4 ?? ns sck low time t sckl 33.4 4 ?? ns output clock rise/fall time ?? 4 ? ns delay from sck high to sc2 (bl) high - slave 5 t tfsbhs -1 ? 29 ns delay from sck high to sc2 (wl) high - slave 5 t tfswhs -1 ? 29 ns t thm t tsm t hm t sm t rfswlm t rfswhm t rfblm t rfsbhm t txhim t txnvm t txvm t txem t tfswlm t tfswhm t tfsblm t tfsbhm t sckl t sckw t sckh first bit last bit sck output sc2 (bl) output sc2 (wl) output std sc0 output sc1 (bl) output sc1 (wl) output srd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
40 DSP56853 technical data preliminary delay from sc0 high to sc1 (bl) high - slave 5 t rfsbhs -1 ? 29 ns delay from sc0 high to sc1 (wl) high - slave 5 t rfswhs -1 ? 29 ns delay from sck high to sc2 (bl) low - slave 5 t tfsbls -29 ? 29 ns delay from sck high to sc2 (wl) low - slave 5 t tfswls -29 ? 29 ns delay from sc0 high to sc1 (bl) low - slave 5 t rfsbls -29 ? 29 ns delay from sc0 high to sc1 (wl) low - slave 5 t rfswls -29 ? 29 ns sck high to std enable from high impedance - slave t txes ?? 15 ns sck high to std valid - slave t txvs 4 ? 15 ns sc2 high to std enable from high impedance (first bit) - slave t ftxes 4 ? 15 ns sc2 high to std valid (first bit) - slave t ftxvs 4 ? 15 ns sck high to std not valid - slave t txnvs 4 ? 15 ns sck high to std high impedance - slave t txhis 4 ? 15 ns srd setup time before sc0 low - slave t ss 4 ?? ns srd hold time after sc0 low - slave t hs 4 ?? ns synchronous operation (in addition to standard external clock parameters) srd setup time before sck low - slave t tss 4 ?? ns srd hold time after sck low - slave t ths 4 ?? ns 1. slave mode is externally generated clocks and frame syncs 2. max clock frequency is ip_clk/4 = 60mhz / 4 = 15mhz for a 120mhz part. 3. all the timings for the essi are given for a non-inverted serial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal sck/sc0 and/or the frame sync sc2/sc1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length table 16: essi slave mode 1 switching characteristics (continued) operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz parameter symbol min typ max units f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
serial communication interface (sci) timing DSP56853 technical data 41 preliminary figure 31. slave mode clock timing 4.12 serial communication interface (sci) timing table 17. sci timing 4 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max )/(32) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns t ths t tss t hs t ss t rfswls t rfswhs t rfbls t rfsbhs t txhis t txnvs t ftxvs t txvs t ftxes t txes t tfswls t tfswhs t tfsbls t tfsbhs t sckl t sckw t sckh first bit last bit sck input sc2 (bl) input sc2 (wl) input std sc0 input sc1 (bl) input sc1 (wl) input srd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
42 DSP56853 technical data preliminary figure 32. rxd pulse width figure 33. txd pulse width 4.13 jtag timing table 18. jtag timing 1, 3 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 120mhz operation, t = 8.33ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/4 the processor rate. 3. parameters listed are guaranteed by design. f op dc 30 mhz tck cycle time t cy 33.3 ? ns tck clock pulse width t pw 16.6 ? ns tms, tdi data setup time t ds 3 ? ns tms, tdi data hold time t dh 3 ? ns tck low to tdo data valid t dv ? 12 ns tck low to tdo tri-state t ts ? 10 ns trst assertion time t trst 35 ? ns de assertion time t de 4t ? ns rxd sci receive data pin (input) rxd pw txd sci receive data pin (input) txd pw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
jtag timing DSP56853 technical data 43 preliminary figure 34. test clock input timing diagram figure 35. test access port timing diagram figure 36. trst timing diagram tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t pw t cy input data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tms t ts t dv t ds t dh trst (input) t trst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
44 DSP56853 technical data preliminary 4.14 gpio timing figure 38. gpio timing figure 37. enhanced once ? debug event table 19. gpio timing 1, 2 operating conditions: v ss = v ssio = v ssa = 0 v, v dd = 1.62-1.98v, v ddio = v dda = 3.0 ? 3.6v, t a = ? 40 to +120 c, c l 50pf, f op = 120mhz 1. in the formulas listed, t = clock cycle. for f op = 120mhz operation and fipb = 60mhz, t = 8.33ns 2. parameters listed are guaranteed by design. characteristic symbol min max unit gpio input period p in 2t + 3 ? ns gpio input high/low period p inhl 1t + 3 ? ns gpio output period p out 2t - 3 ? ns gpio output high/low period p outhl 1t - 3 ? ns de t de gpio inputs gpio outputs p inhl p inhl p in p outhl p outhl p out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
package and pin-out information DSP56853 DSP56853 technical data 45 preliminary part 5 packaging 5.1 package and pin-out information DSP56853 this section contains package and pin-out information for the 128-pin lqfp configuration of the DSP56853. figure 39. top view, DSP56853 128-pin lqfp package pin 103 pin 1 pin 39 pin 65 mosi sck ss v ddio v ssio rd wr a1 a2 a3 v dd v ss moda modb modc v ddio v ssio irqa irqb v dda v ssa xtal extal a4 motorola DSP56853 orientation mark rsto reset hd3 hd4 hd5 hd6 hd7 v ddio v ssio a8 a9 a10 a11 v dd v ss de trst tdo tdi tms tck v ddio v ssio a12 txd1 rxd1 v ssio v ddio v ddio d5 d4 d3 d2 d1 hrwb ha2 ha1 ha0 v ss v dd v dd cs3 cs2 cs1 cs0 v ssio d0 v ddio a20 a13 a14 a15 v ddio v ss v dd v ss tio3 tio2 tio1 v ddio tio0 v ssio hds hcs hreq hack d6 d7 d8 d9 d10 v dd v ss v ddio v ssio std0 srd0 sck0 sc00 sc01 sc02 d11 d12 v ddio v ssio d13 d14 d15 miso a5 a6 a7 hd0 hd1 hd2 a0 a19 a18 a17 a16 txd0 rxd0 clko v ssio f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
46 DSP56853 technical data preliminary table 20. DSP56853 pin identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1miso 33 clko 65 rxd0 97 tio3 2mosi 34 rsto 66 txdo 98 tio2 3sck 35 reset 67 a16 99 tio1 4ss 36 hd3 68 a17 100 v ddio 5v ddio 37 hd4 69 a18 101 tio0 6v ssio 38 hd5 70 a19 102 v ssio 7rd 39 hd6 71 a20 103 hds 8wr 40 hd7 72 v ddio 104 hcs 9a0 41 v ddio 73 d0 105 hreq 10 a1 42 v ssio 74 v ssio 106 hack 11 a2 43 a8 75 cs0 107 d6 12 a3 44 a9 76 cs1 108 d7 13 v dd 45 a10 77 cs2 109 d8 14 v ss 46 a11 78 cs3 110 d9 15 moda 47 v dd 79 v dd 111 d10 16 modb 48 v ss 80 v dd 112 v dd 17 modc 49 de 81 v ss 113 v ss 18 v ddio 50 trst 82 ha0 114 v ddio 19 v ssio 51 tdo 83 ha1 115 v ssio 20 irqa 52 tdi 84 ha2 116 std0 21 irqb 53 tms 85 hrwb 117 srd0 22 v dda 54 tck 86 d1 118 sck0 23 v ssa 55 v ddio 87 d2 119 sc00 24 xtal 56 v ssio 88 d3 120 sc01 25 extal 57 a12 89 d4 121 sc02 26 a4 58 a13 90 d5 122 d11 27 a5 59 a14 91 v ddio 123 d12 28 a6 60 a15 92 v ddio 124 v ddio 29 a7 61 v ddio 93 v ssio 125 v ssio 30 hd0 62 v ssio 94 rxd1 126 d13 31 hd1 63 v ss 95 txd1 127 d14 32 hd2 64 v dd 96 v ss 128 d15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
package and pin-out information DSP56853 DSP56853 technical data 47 preliminary figure 40. 128-pin lqfp mechanical information notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b, and d to be determined at datum plane h. 5. dimensions d and e to be determined at seating plane c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions d1 and e1 do include mold mismatch and are determined at datum plane h. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.35. dim millimeters min max a --- 1.60 a1 0.05 0.15 a2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 d 22.00 bsc d1 20.00bsc e0.50 bsc e 16.00 bsc e1 14.00 bsc l 0.45 0.75 l1 1.00 ref l2 0.50 ref s 0.20 --- r1 0.08 --- r2 0.08 0.20 0 0 o 7 o 01 0 o --- 02 11 o 13 o case outline - 1129-01 128 103 38 102 65 64 39 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
48 DSP56853 technical data preliminary part 6 design considerations 6.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: t j = t a + (p d x r ja ) where: t a = ambient temperature c r ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: r ja = r jc + r ca where: r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb), or otherwise change the thermal dissipation capability of the area surrounding the device on the pcb. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. a complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junction to board thermal resistance. use the value obtained by the equation (t j ? t t )/p d where t t is the temperature of the package case determined by a thermocouple. as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical design considerations DSP56853 technical data 49 preliminary on the case of the package will estimate a junction temperature slightly hotter than actual. hence, the new thermal metric, thermal characterization parameter, or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 6.2 electrical design considerations use the following list of considerations to assure correct dsp operation: provide a low-impedance path from the board power supply to each v dd pin on the dsp, and from the board ground to each v ss (gnd) pin. the minimum bypass requirement is to place six 0.01 ? 0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the ten v dd /v ss pairs, including v dda /v ssa. ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead. use at least a four-layer printed circuit board (pcb) with two inner layers for v dd and gnd. bypass the v dd and gnd layers of the pcb with approximately 100 f, preferably with a high- grade capacitor such as a tantalum capacitor. because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and gnd circuits. all inputs must be terminated (i.e., not allowed to float) using cmos levels. take special care to minimize noise levels on the v dda and v ssa pins. when using wired-or mode on the spi or the irqx pins, the user must provide an external pull- up device. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
50 DSP56853 technical data preliminary designs that utilize the trst pin for jtag port or enhance once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer products, should tie these pins together. the internal por (power on reset) will reset the part at power on with reset asserted or pulled high but requires that trst be asserted at power on. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical design considerations DSP56853 technical data 51 preliminary part 7 ordering information table 21 lists the pertinent information needed to place an order. consult a motorola semiconductor sales office or authorized distributor to determine availability and to order parts. table 21. DSP56853 ordering information part supply voltage package type pin count frequency (mhz) order number DSP56853 1.8v, 3.3v low-profile quad flat pack (lqfp) 128 120 DSP56853fg120 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 home page: http://motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2004 DSP56853/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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